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E2C0024-27-Y4 Semiconductor
Semiconductor MSC1230
This version: Nov. 1997 MSC1230 Previous version: Jul. 1996
111-Bit 2/3-Duty Controller/Driver with Digital Dimming Function
GENERAL DESCRIPTION
The MSC1230 is a Bi-CMOS display driver with digital dimming function. It enables switching between 1/3-duty vacuum fluorescent (VF) display tube and universal VF display tube by pin control. The MSC1230 consists of a 112-bit shift register, a 111-bit latch, a 10-bit digital dimming circuit, 37 segment drivers, and 3 grid drivers. The MSC1230 provides an interface with a microcomputer only by three signal lines: CS, DATA-IN, and CLOCK. By using the chip select function, the DATA-IN and CLOCK signal lines can be shared by other peripheral circuits.
FEATURES
* * * * * * Power supply voltage : VDD=8 V to 18 V (built-in 5 V regulator for logic circuit) Operating temperature range : Ta=-40 C to +85 C 37-segment driver outputs : IOH=-6 mA at VOH = VDD -0.8 V 3-grid driver outputs : IOH=-30 mA at VOH = VDD -0.8 V Built-in digital dimming circuit (10-bit resolution) Switchable between 1/3-duty VF display tube and universal VF display tube* When SEL pin is left open : Selects universal VF display tube (The grids GRID1, GRID2, and GRID1+GRID2 are turned on repeatedly in this order) When SEL pin is used at 0 V : Selects 1/3-duty VF display tube (The grids GRID1, GRID2, and GRID3 are turned on repeatedly in this order) * Built-in oscillation circuit (external R and C) * Built-in Power-On-Reset circuit * Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K)(Product name: MSC1230GS-2K) * A universal VF display tube is a display tube for which, like a gate array, the user can freely design characters and patterns on the master layer (grid). (Pattern can be created without gaps between grids.) Since the outline dimensions of the display tube and the grid layout are predetermined, desired patterns can be displayed in a short time. The universal VF display tube is used for the display parts for audio equipment, household appliances, and automobile equipment.
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Semiconductor
MSC1230
BLOCK DIAGRAM
SEG37 VDD1 VDD2 DGND 5V REG. POR LGND 37 111 CS Control Circuit DATA-IN CLOCK 112 111 107106 75 74 111-bit Latch 111-bit data 97 96 112-bit Shift Register 10-bit data 10-bit Latch 37 38 37 37 5V POR 37 111 37-Segment Control 37-bit Segment Driver 37bit data
SEG1
GRID3
GRID1
VDD3
3-bit Grid Driver VDD=8 - 18V 1 VCC=5.0V (Regurator)
1
1
10-bit data OSC0 OSC1 OSC 5V 10-bit Digital Diming
SEL 112bits=0: Digital Dimming Mode 112bits=1: VF Data Input Mode
Timing Generator
POR
INPUT AND OUTPUT CONFIGURATION l Schematic Diagram 1 of l Schematic Diagram 2 of l Schematic Diagram of Logic Portion Input Circuit Logic Portion Input Circuit Driver Output Circuit
VDD (5V Reg.)
VDD (5V Reg.)
VDD
VDD
INPUT
COLn
OUTPUT
GND
GND
GND
GND
GND
GND
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Semiconductor
MSC1230
PIN CONFIGURATION (TOP VIEW)
SEG19 1 SEG20 2 SEG21 3 SEG22 4 SEG23 5 SEG24 6 SEG25 7 SEG26 8 SEG27 9
SEG28 10 SEG29 11
SEG30 12 SEG31 13 SEG32 14
SEG33 15
SEG34 16
SEG35 17
SEG36 18
SEG37 19
NC 20 LGND 21
OSC1 23
OSC0 24
SEL 25
NC 22
CS 26
CLOCK 27
NC: No connection 56-Pin Plastic QFP
DATA-IN 28

56 SEG18 55 SEG17 54 SEG16 53 SEG15
46 SEG13
52 SEG14
45 SEG12
44 SEG11
43 SEG10
49 DGND
51 VDD2
47 VDD1
50 NC
48 NC
42 SEG9 41 SEG8 40 SEG7 39 SEG6 38 SEG5 37 SEG4 36 SEG3 35 SEG2 34 SEG1 33 NC 32 GRID1 31 GRID2 30 GRID3 29 VDD3
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Semiconductor
MSC1230
PIN DESCRIPTION
Pin 34 to 46, 52 to 56, 1 to 19 30 to 32 25 Symbol SEG1 to 37 Type Decription O Output pins for segment signals for driving VF display tube.
GRID1 to 3 SEL
O I
Output pins for grid signals for driving VF display tube. The GRID3 output is not used when the universal VF display tube is used. When at a "L" level, this pin selects 1/3-duty VF display tube. When at a "H" level (or when used in the open state), this pin selects universal VF display tube. Pin for series data input from microprocessor. Data is input to the shift register on the rising edge of the CLOCK signal. Serial clock input pin. Data is input through the DATA-IN pin at the rising edge of the serial clock. RC oscillator connecting pins. Connect a resistor between the OSC1 and OSC0 pins and a capacitor between the OSC0 pin and the ground. Chip select input pin. Circuit operation is valid when this pin is at a "L" level. Power supply pins. When using these pins, connect each of them to the power supply. Ground pins for driver and logic. These pins can be connected with each other when they are used.
28 27
DATA-IN CLOCK
I I
24 23 26 47 51 29 49 21
OSC0 OSC1 CS VDD1 VDD2 VDD3 DGND LGND
I O I
-- -- --
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Semiconductor
MSC1230
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Storage Temperature Power Dissipation Symbol VDD VIN TSTG PD Condition -- All inputs -- Ta=85C Ratings -0.3 to +20 -0.3 to +6.0 -65 to +150 400 Unit V V C mW
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage High Level Input Voltage (1) High Level Input Voltage (2) Low Level Input Voltage (1) Low Level Input Voltage (2) Clock Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDD VIH1 VIH2 VIL1 VIL2 fC fOSC fFR Top Condition -- All inputs except OSC0 OSC0 All inputs except OSC0 OSC0 -- R=4.7 kW, C=10 pF fOSC=3.2 MHz -- Min. 8 3.8 4.5 0.0 0.0 -- -- -- -40 Typ. -- -- -- -- -- -- 3.2 260 -- Max. 18 5.5 5.5 0.8 0.5 250 -- -- 85 Unit V V V V V kHz MHz Hz C
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Semiconductor
MSC1230
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=-40 to +85C, VDD=8 to 18V) Parameter "H" Input Voltage (1) "H" Input Voltage (2) "L" Input Voltage (1) "L" Input Voltage (2) "H" Input Current (1) "H" Input Current (2) "L" Input Current (1) "L" Input Current (2) "H" Output Voltage (1) "H" Output Voltage (2) *1 *2 *1 *2 *3 *4 *3 *4 *5 *6 Symbol VIH1 VIH2 VIL1 VIL2 IIH1 IIH2 IIL1 IIL2 VOH1 VOH2 VOL1 "L" Output Voltage *7 VOL2 VOL3 Supply Current IDD Condition -- -- -- -- VIH=5 V VIH=5 V VIL=0 V VIL=0 V VDD=9.5 V IOH1=-6 mA VDD=9.5 V IOH2=-30 mA VDD=9.5 V IOL1=500 mA VDD=9.5 V IOL2=200 mA VDD=9.5 V IOL3=2 mA fosc=3.2 MHz no Load Min. 3.8 4.5 0.0 0.0 -5 -200 -5 -0.6 VDD -0.8 VDD -0.8 -- -- -- -- Max. 5.5 5.5 0.8 0.5 5 200 5 -0.1 -- -- 2 1 0.3 13 Unit V V V V mA mA mA mA V V V V V mA
*1 *2 *3 *4 *5 *6 *7
All input pins except OSC0 OSC0 pin CS, CLOCK and DATA-IN pins SEL pin SEG1 to SEG37 pins GRID1 to GRID3 pins SEG1 to SEG37 and GRID1 to GRID 3 pins
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Semiconductor AC Characteristics
Parameter Oscillation Frequency External Input Frequency into OSC0 Clock Frequency Clock Pulse Width DATA Setup Time DATA Hold Time CS Pulse Width CS Off Time CS Setup Time CS-Clock Time CS Hold Time Clock-CS Time CS-All Data Output Delay Slew Rate (All Drivers) CS Time at Power-on Hold Time at Power-off Rise Time at Power-on Symbol fOSC fOSCI fC tCW tDS tDH tCSW tCSL tCSS tCSH tODS tR tPCS tPOF tPRZ Condition R=4.7 kW , C=10 pF External input only -- -- -- -- -- -- -- -- CI=100 pF CI=100 pF t=20% to 80% or 80% to 20% -- When monuted on the unit VDD=0.0 V When monuted on the unit
MSC1230
(Ta=-40 to +85C, VDD=8 to 18V) Min. Max. Unit 2 2.7 -- 1.3 1 200 8 32 2 2 -- -- 300 5 -- 4.4 3.7 250 -- -- -- -- -- -- -- 8 5 -- -- 100 MHz MHz kHz ms ms ns ms ms ms ms ms ms ms ms ms
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Semiconductor
MSC1230
CS tcss CLOCK tDS DATA-IN tDH
tcsw fc tcw tDS tDH tcw tDS tCSH tDH
tCSL
3.8V 0.8V 3.8V 0.8V 3.8V 0.8V
VALID
VALID
VALID
Figure 1. Data Input Timing
CS tODS SEG1-37 GRID1-3 tR
tCSW tODS tR
3.8V 0.8V 80% 20%
Figure 2. SEG or GRID Driver Output Timing
VDD1, 2, 3 tPCS CS tPOF
tPRZ
8V 0V 3.8V 0.8V
Figure 3. Power-on Timing
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Semiconductor
MSC1230
FUNCTIONAL DESCRIPTION
Power-on Reset When power is turned on, the IC is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: - The contents of the shift registers and latches are set to "0". - The digital dimming duty cycle is set to "0". Data Input Data input to the DATA-IN pin is valid only when the CS pin is at a "L" level. The input data to DATA-IN is shifted into the shift registers on the rising edge of the clock. The data is automatically loaded to the latches on the rising edge of the CS pin. When M0 = "1", the IC enters the display data input mode and a total of 112 bits of data are input. When M0 = "0", the IC enters the digital dimming data input mode and a total of 16 bits of data are input. [Data Format] 1) Display Data Input Mode Input Data : VF Display Data : Mode Select Data (M0) :
Bit 112 111 110 .... M0 D111 D110 .... Mode Data (1 bit)
112 bits 111 bits 1 bit
.... .... 4 D4 3 D3 2 D2 1 D1 First in
97 96 95 94 93 92 91 D97 D96 D95 D94 D93 D92 D91 Display Data (111 bits)
2) Bit correspondence between segment outputs and shift registers
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEG 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 G1 BIT 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 G2 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 G3
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Semiconductor 3) Input Format for VF data
Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 c7 D8 D16 D24 D32 D40 D48 D56 D64 D72 D80 D88 D96 D104 M0 c6 D7 D15 D23 D31 D39 D47 D55 D63 D71 D79 D87 D95 D103 D111 c5 D6 D14 D22 D30 D38 D46 D54 D62 D70 D78 D86 D94 D102 D110 c4 D5 D13 D21 D29 D37 D45 D53 D61 D69 D77 D85 D93 D101 D109 c3 D4 D12 D20 D28 D36 D44 D52 D60 D68 D76 D84 D92 D100 c2 D3 D11 D19 D27 D35 D43 D51 D59 D67 D75 D83 D91 D99 c1 D2 D10 D18 D26 D34 D42 D50 D58 D66 D74 D82 D90 D98 D106 c0 D1 D9 D17 D25 D33 D41 D49 D57 D65 D73 D81 D89 D97 D105
MSC1230
D108 D107
4) Digital Dimming Data Input Mode This data consists of 10 bits. The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99%) for each grid. The 10-bit digital dimming data is input from the LSB. Input Data : 16 bits Digital Dimming Data : 10 bits Mode Select Data : 1 bit
Bit 112 111 M0 xx Mode Data (1bit) (MSB) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 110 xx 109 xx 108 xx 107 xx 106 105 10 9 MSB 104 8 103 7 102 6 101 5 100 4 99 3 98 2 97 1 LSB First in
Dimming Data (10 bits)
INPUT DATA 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1
(LSB) DUTY CYCLE 0 1 0 1 0/1024 1/1024 1016/1024 1016/1024
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Semiconductor 5) Input Format for Dimming Data
MSC1230
Byte 1 2
c7 8 M0
c6 7 xx
c5 6 xx
c4 5 xx
c3 4 xx
c2 3 xx
c1 2 10
c0 1 9
6) Function Mode
M0 0 1
FUNCTION Display Data Input Mode Digital Dimming Data Input Mode
GRID/SEG Driver Operation and Digital Dimming Figures 4 and 5 show the timing for the GRID and SEG drivers in universal VFD mode and 1/3 duty VFD mode, respectively. Figure 6 shows an example of timing for digital dimming operation in 1/3 duty VFD mode. (When the duty cycle in the dimming data is 508/1024)
GRID1 3072 bit time (1 display cycle)
GRID2
GRID3 3 bit time SEG1-37 1019 bit time * 1 bit time=4/fOSC 5 bit time 1024 bit time 8 bit time
Figure 4. Duty Cycle Timing (Universal VFD Mode)
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Semiconductor
MSC1230
GRID1 3072 bit time (1 display cycle)
GRID2
GRID3 3 bit time SEG1-37 1019 bit time 5 bit time 1024 bit time 8 bit time
Figure 5. Duty Cycle Timing (1/3 Duty Mode)
508 GRID1
508
3072 bit time GRID2
GRID3 511 SEG1-37 508 1024
Figure 6. Duty Cycle Timing (1/3 Duty Mode)
(When digital dimming data is changed from 3F8H to 1FFH) 1016 bit time 511 bit time
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Semiconductor
MSC1230
PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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